EDAUtils
Semiconductors - Toronto, Ontario, Canada
EDAUtils Employees
EDAUtils Details
EDAUtils provides a correct-by-construct IP packaging and Integration Methodologies along with a set of utilities that transforms the quality and efficiency of your SoC designs in order of magnitudes. Many of the tools and utilities which often is not available as product from EDA Vendors. Though these tools are not very compute intensive and neither these are algorithmically very challenging but most of the frontend designers often need many of these during their design cycle. All these applications are highly configurable and also available as Library to meet custom requirements. The entire EDAUtils' solutions is classified into the below three categories.Baya- SoC Integration Platform------------------------------------------Developed in collaboration with semiconductor companies servicing the consumer market. The objective of this automation is to reduce the RTL Generation effort for FPGA, SubSystem or SoC Platform and derivative designs by more than an order of magnitude, while also dramatically reducing the level of human error in IP Integration and Hierarchy Manipulation ...IP-XACT 1685-------------------This IP-XACT Based IP Packaging provides intuitive GUI to create Components and Bus Interfaces, HW/SW Registers and Fields, Memory-Map and bunch of generators including C Header files, UVM Registers, Documents ...RTL Utilities-----------------This is collection of a number of utilities like Testbench generators, hierarchy manipulation through instance group/ungroup, comparing module/entity interfaces, Verilog and VHDL wrapper generators, Verilog and VHDL Parsers, verilog2vhdl, vhdl2verilog, verilog2ipxact, verilog2systemc ...
EDAUtils Technologies
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Apache
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