Suresh Kotthala
Senior lead physical design engineer at AdeptChips - San Jose, California, United States
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AdeptChips
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Adept is a 7+ year old organization with primary focus being on ASIC Design Solutions. We are specialized in Design Verification, DFT, Physical Design domains. Our focus has been on-time first time right. We have a proven track record of taping out designs with complexities ranging from 40M to 100M gate-count and in various technologies 7nm, 10nm, 14nm, 16nm, 28nm, 32nm, 45nm and 65nm. The flows that have been used in implementing these chips vary based on the complexity and nature of the design. We are good at taking designs and optimizing area and coming-up with best-bounding box for the chip and coordinating with package-team for better package & aspect-ratio of the chip. This will result in optimized "GDPW" (Gross dies per wafer). Design Verification o SoC Verification o IP / SubSystem Verification o Random Verification with SV-UVMDesign For Test (DFT) o Scan Insertion o MBIST o BSD o ATPG Pattern Generation & SimulationPhysical Design o Flat fullchip implementation (Netlist to GDSII) o Hierarchical fullchip implementation (Netlist to GDSII) o Block level implementation (Netlist to GDSII)Embedded Software o Driver Development o Characterization